1. Technical Field
Embodiments disclosed herein are related to protecting an analog-to-digital converter from excessive signals.
2. Related Art
Analog-to-digital converters (ADCs) are important in modern electronics, as they may be used to convert a continuous physical quantity represented by an analog signal to a digital representation that may approximate the amplitude of the analog signal. ADCs may typically convert the analog signal by periodically sampling and quantizing the analog signal to produce a sequence of digital values that correspond to a discrete-time and discrete-amplitude digital signal. One type of ADC is a pipeline or pipelined ADC, which uses multiple steps of conversion in successive stages to produce a digital signal.
Most ADCs may be specified to work within a particular input signal range, referred to as the full scale range, and a system having an ADC may include automatic gain control (AGC) to control the input signal to be within this range. Since the sensitivity of the ADC may be closely related to the signal-to-noise ratio (SNR), the AGC may be typically set so that the input signal is very close to the full scale range of the ADC to improve the SNR. However, when the input signal increases suddenly, such as may occur when a system including the ADC is first powered on, the AGC is typically not fast enough to control the input signal such that the ADC receives an input signal that exceeds the full scale range. For applications where the ADC is used to convert an input voltage, receiving an input signal that is an input voltage that exceeds the full scale range can cause problems.
For example, when the input signal, which may be an input voltage, exceeds the full scale range, the internal voltages of the ADC may exceed the limits permitted by the manufacturing process and may cause transistors of the ADC to experience a hot carrier effect, which may damage and eventually destroy the transistors of the ADC. For most modern submicron manufacturing processes, this is particularly problematic because robustness and protection is sacrificed for increased speed. Moreover, for pipeline or pipelined ADCs, the high input voltage may be propagated to subsequent stages, and can damage more than just the first or initial stage. As another example, when an ADC recovers from a saturation state, calibration information used to calibrate the ADC during the saturation state is skewed such that the ADC is improperly calibrated after the recovery as long as the skewed calibration information determined during the saturation state are propagated. For pipeline or pipelined ADCs, errors due to skewed calibration information may be further propagated to other stages of the ADC, resulting in further errors.
Conventional ADCs may use an external input clamping buffer to limit or “clamp” the input signal to be close to the maximum full scale signal. However, such external clamping buffers have some drawbacks. For example, extra cost and die space is required to add the extra integrated circuit required for the external clamping buffer. The external clamping buffer may also add in additional noise or additional distortion to the input signal, resulting in noise or distortion propagating through the ADC. In addition, because the full scale signal of the ADC will vary based on such factors as temperature and component matching, the external clamping buffer may have to adjust the clamping level, which may lead to a reduced level of the input signal compared to the full scale signal and, consequently, a reduced SNR.